1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of internal voltage generating circuits.
Priority is claimed on Japanese Patent Application No. 2009-152058, filed Jun. 26, 2009, the content of which is incorporated herein by reference.
2. Description of Related Art
A semiconductor device, such as a DRAM (Dynamic Random Access Memory) which is a typical example of the semiconductor device, generally includes an internal voltage generating circuit that generates a voltage different from a power voltage VDD supplied from the outside and a ground voltage VSS.
For example, the semiconductor device includes a substrate voltage generating circuit (back-bias generator) that applies a negative substrate voltage to a P-type semiconductor substrate in which N-channel MOS transistors are formed. The application of the back bias to the substrate controls the parasitic capacitance between the semiconductor substrate and transistors and threshold voltages (Vt) of the transistors, thereby stabilizing operations of the semiconductor device.
In the semiconductor device, such as a DRAM, when the level of a power voltage VDD is stored in a capacitive element of a memory cell, a selecting transistor connected to the memory cell is turned on and charge is supplied from a bit line to the capacitive element through the selecting transistor. In this case, it is necessary to apply a voltage that is higher than the voltage VDD by the threshold voltage of the selecting transistor to a gate terminal. Therefore, a boosted voltage generating circuit is provided.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2005-196936 discloses a semiconductor device including the internal voltage generating circuit. The semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2005-196936 has a first volatile memory function and a second non-volatile memory function. The semiconductor device replaces volatile memory data with non-volatile memory data. The semiconductor device replaces non-volatile memory data with volatile memory data. The semiconductor device includes a plurality of internal voltage generating circuits that achieves the first function and the second function. The semiconductor device changes an output voltage supplied to a load circuit A according to the function mode. The function mode is the operation modes, such as a volatile (DRAM) access mode to the memory cell and a non-volatile access mode (program, recall, back-up, or erase mode). Therefore, the semiconductor device includes a mode control unit that generates control signals for each function mode and a level selector circuit that connects an internal voltage generating circuit and a load circuit A according to the operation mode on the basis of the control signals from the mode control unit. This can be referred to in FIG. 4 in Japanese Unexamined Patent Application, First Publication, No. JP-A-2005-196936. According to this configurations, in the semiconductor device, after power is turned on, the first function that performs read and write accesses at a high speed is performed to detect the temporary interruption of the power supply, and the function is changed from the first function to the second function to store volatile memory data as non-volatile memory data, thereby preventing the loss of data.
The semiconductor devices (including a semiconductor chip) as manufactured have different characteristics of the internal voltage generating circuit and the load circuit A due to the characteristics of transistors caused by manufacturing conditions, that is, variations on manufacturing processes. In the semiconductor device according to the related art, the correspondence between the internal voltage generating circuit and the load circuit A is determined according to the operation mode, regardless of the characteristics of the load circuits that are different for each semiconductor device. It is difficult to allocate the internal voltage generating circuit that is most suitable for the characteristics of the internal voltage generating circuit and the characteristics of the load circuits.
In the semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2005-196936, switching control between a plurality of internal voltage generating circuits and a plurality of load circuits is performed according to the function mode of the semiconductor device. However, when switching control is performed, the switching conditions are not determined according to the characteristics of each semiconductor device.
In the switching control of each of the manufactured semiconductor devices according to the related art, only a switching operation corresponding to the function mode of the product is performed, and it is difficult to test the characteristics of the internal voltage generating circuits or the load circuits while changing combinations of the voltage generating circuits and the load circuits. Therefore, it is difficult to allocate the load circuit A that is most suitable for the characteristics of the internal voltage generating circuit, or it is difficult to allocate the internal voltage generating circuit that is most suitable for the characteristics of the load circuit A. In the examination test after the semiconductor device is manufactured, in some cases, the semiconductor device does not satisfy an examination test standard due to the characteristics, for example, capability and the amount of leakage current, of the internal voltage generating circuit and the load circuit A. The semiconductor device does not satisfy the examination test standard and is determined to be defective. As a result, product yield is not improved, and it is difficult to reduce manufacturing costs.
In addition, in some cases, the system including the semiconductor device is performed in the high-speed mode or the low-speed mode. For example, a CPU, an MCU, or a DSP device is operated in the high-speed mode or the low-speed mode by, for example, the clock-up of the system defined by the BIOS, and a memory device is operated in the high-speed mode or the low-speed mode according to CAS latency or the frequency of a synchronization signal (external clock signal CLK). In general, when the semiconductor device is operated at a high speed, the leakage current of the semiconductor transistor increases and the noise of the semiconductor chip increases. It is preferable that the internal power voltage generating circuits and the load circuits that are most suitable for the characteristics of the internal voltage generating circuits and the characteristics of the load circuits in each semiconductor device be allocated in relation to the internal operation speed of the semiconductor device. Similarly, the allocation may be performed in relation to the power voltage or the temperature of the semiconductor. This is because the internal operation speed of the semiconductor or the leakage current is changed in relation to the power voltage or the temperature of the semiconductor.